The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to an interconnect structure containing an electromigration and stress migration enhancement liner located between a patterned interconnect dielectric material and a diffusion barrier. The present disclosure also relates to a method of forming such an interconnect structure.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, -based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than silicon dioxide.
In typical interconnect structures, good liner coverage has been a challenge. This is particularly true in a via of a dual damascene interconnect structure. Problems associated with poor liner coverage include: (i) early device failure for via depletion electromigration; (ii) early device failure of stress migration with plate above type structures; and (iii) degradation of the Blech effect. This effect, also known as stress-induced backflow, was coined after IA Blech, who first reported this phenomenon for aluminum metal lines. The Belch effect can be summarized as follows: as the metal ions move toward the anode end of the metal line, stress build-up occurs opposing the electron flow, thus constraining void growth which can lead to device failure.
There is a need for providing a method and structure which avoids the aforementioned problems associated with prior art interconnect structures, without negatively effecting time-dependent-dielectric breakdown (TDDB) performance and/or increasing the resistance of the via. By “TDDB” it is meant that overtime the dielectric material of the interconnect structure begins to fail. The failure of the dielectric material may be caused by intrinsic means or by defects that are formed on the surface of the interconnect dielectric during the course of preparing the interconnect structure.